Interactive method of optimum lsi layout including considering lsi chip size, test element groups, and alignment marks

ABSTRACT

The invention provides a method of LSI layout which is used in the stage of making a LSI layout plan for each of a plurality of LSI chips before entering in the design of masks, wherein there are included a step of judging whether or not all the LSI chips can be arranged on a single wafer along with other objective components, based on a given LSI chip size and referring to the information on the other objective components, or a step of calculating a LSI chip yield per water and/or a manufacturing cost per LSI chip. Therefore, a LSI layout designer can make a quick decision with ease within a limited LSI development term, as to how much the LSI chip size is to be downsized for economical production of the LSI chip, referring to the results of the above judgement and calculation.

BACKGROUND OF THE INVENTION

[0001] This invention relates to a method of LSI layout, more particularly to a method of LSI layout, which makes it possible to achieve an optimum LSI layout by taking account of a LSI chip yield per wafer (the number of LSI chips which can be arranged on a single wafer) and a manufacturing cost per LSI chip a well.

[0002] Generally, in the initial stage of setting up a LSI layout on a wafer, a so-called floor plan is made at first. The object of this floor plan is to elaborate how to reduce the area occupied by respective LSI chips and also how to improve the performance thereof, thereby roughly setting up the arrangement of LSI chips on the wafer in advance of actually arranging LSI chips and wires distributed thereto on the wafer.

[0003] Conventional basic way of thinking to the floor plan has stood on the premise that reduction of an individual LSI chip size should naturally result in increase in the number of LSI chips which can be arranged on a single wafer. However, in the actual field of LSI chip production, the number of LSI chips which can be arranged on a single wafer depends not only on the size of the LSI chip, but depends on other factors and conditions, for instance location of various alignment marks which are formed on the wafer and referred to when executing the over-printing of various mask patterns by using a light exposure device or an aligner, placement of TEG (Test Element Group) which is mounted on each of LSI chips for evaluation of respective circuits and processes, and so forth. Therefore, reduction of the chip size should not always result in increase in the number of chips which can be arranged on each wafer i.e. the LSI chip yield per wafer. Accordingly, even though reduction of the LSI chip size could be done by spending a huge amount of man-hour for the LSI layout design, it might happen that the LSI chip yield is left unchanged after all, or that the LSI chip yield is rather decreased contrarily to the expectation, because of restrictions over the aligner as used, restrictions over location of various alignment marks and TEG, and others. This has been raised as a problem to be solved.

[0004] Also, in the prior art method, there has happened sometime such a case that it is revealed, during the design work of the mask after once completing the LSI layout, that various marks and TEG can not be located on the mask. In the worst case as such, the LSI layout can not but be revised, which results in a large extension of the time period for development of a new LSI.

[0005] As mentioned above, in the prior art method of LSI layout, the design of LSI layout is carried out focusing only on a LSI chip itself, and the arrangement of LSI chips in association with the mask is left out of consideration, so that it happens that reduction of the LSI chip size fails to result in reduction of the manufacturing cost, or that it is revealed, during the design work of masks after completion of the LSI layout, that the LSI chip arrangement satisfying an aimed LSI chip yield per wafer can not be realized. These have been raised as problems to be obviated.

[0006] Accordingly, the present invention has been made in view of the above-mentioned problems involved in the prior art method of LSI layout, and an object of the invention is to provide a novel and improved method of LSI layout which makes it possible to determine at the stage of designing a LSI layout how much the LSI chip size is to be reduced for realizing an optimum LSI layout by taking account of the LSI chip yield per wafer and the manufacturing cost per LSI chip.

[0007] Another object of the invention is to provide a novel and improved method of LSI layout which makes it possible to determine in the stage of designing a LSI layout whether or not LSI chips can be arranged on the wafer, thereby eliminating the step of modifying the LSI layout which might be caused depending on the result of the mask design.

SUMMARY OF THE INVENTION

[0008] In order to solve the problems as mentioned above, the present invention provides a method of LSI layout which is used in the stage of making a LSI layout plan for each of a plurality of LSI chips before entering in the design of masks, wherein there is included a step of judging whether or not all the LSI chips can be arranged on a single wafer along with other objective components (i.e. those which are to be arranged with LSI chips on the same wafer), based on a given LSI chip size and referring to the information on the other objective components.

[0009] According to the constitution of the above method, it becomes possible, in the LSI layout work before entering in the mask design, to judge whether or not the LSI layout can be actually realized, based on the currently given LSI chip size. Therefore, this eliminates the step of modifying the LSI layout which might be caused depending on the result of the mask design.

[0010] Furthermore, in case of judging the possibility of arrangement of LSI chips and other objective components on the wafer, it is preferable to take account of the information on objective components other than the LSI chip, such as the information on various marks, the information on TEG, and so forth.

[0011] In order to solve the problems as mentioned above, the present invention still provides a method of LSI layout which is used in the stage of making a LSI layout plan for each of a plurality of LSI chips before entering in the design of masks, wherein there are included steps of calculating a LSI chip yield per wafer based on the given LSI chip size, and/or a step of calculating a manufacturing cost per LSI chip based on the given LSI chip size.

[0012] According to the constitution of the above-mentioned method, it becomes possible, during the LSI layout work, to take account of the LSI chip yield per wafer and/or the manufacturing cost per LSI chip, so that it can be judged what size of the LSI chip is optimum for low cost manufacturing of LSI chips. Therefore, this contributes to enhancement of efficiency in development procedure of the LSI.

[0013] A given LSI chip size used as the base of judgement in the method according to the invention, may be a temporary LSI chip size which is calculated based on the basic design data, or may be a real LSI chip size employed in the state wherein arrangement and wiring of all the LSI chips and other objective components on the wafer have been completed.

[0014] Furthermore, as the method of the invention can be constituted in such a manner that a plurality of LSI chip sizes may be given, it become possible to judge the possibility of arranging all the LSI chips and other objective components on one wafer on each LSI chip size. If the method is constituted such that the LSI chip yield per wafer or the manufacturing cost per LSI chip is calculated with regard to each LSI chip size, the designer may determine which LSI chip size is optimum for the LSI layout.

[0015] The aforementioned objects, features and advantages of the invention will become more clear from the following detailed description of the invention, taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the drawings:

[0017]FIG. 1 is a block diagram showing a schematic constitution of a CAD device to which a method of LSI layout of the invention is applicable.

[0018]FIG. 2 is a flow chart showing steps of executing a first preferred embodiment of a method of LSI layout according to the invention.

[0019]FIG. 3 is a flow chart showing steps of executing a second preferred embodiment of a method of LSI layout according to the invention.

[0020]FIG. 4 is a flow chart showing steps of executing a third preferred embodiment of a method of LSI layout according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0021] Preferred embodiments of the method of LSI layout according to the invention will now be described in detail referring to the accompanying drawings.

[0022] Referring to FIG. 1, there will be first described a schematic constitution of a CAD device 100 which is used for making a floor plan for executing the method of LSI layout according to the invention. A control device 102 collects necessary information from a variety of databases 104, 106 a, 106 b, 106 c . . . 108, and performs necessary operation based on the collected information according to the instruction by a LSI layout designer, and finally reports a result of the operation to the designer in the form of a display on a display device 110 such as a CRT. This report includes the LSI layout and other necessary information, such as a LSI chip yield per wafer and a manufacturing cost per LSI chip. The designer then enters in the next step with reference to the displayed information. The above-mentioned constituents include nothing but the most essential constituents which are inevitable for a CAD device for use in the floor plan. Accordingly, it is naturally allowed to additionally employ various peripheral equipment, in order to set up a more practical system.

[0023] The LSI layout designer refers to and uses various databases when he designs a LSI layout. To describe in terms of an example shown in FIG. 1 for instance, he uses the basic design information database 104 which stores data relating to various design elements necessary for designing the LSI layout, the process information database 106a which stores data relating to various process conditions necessary for actual LSI production, the mark information database 106b which stores data relating to various alignment marks to be referred to by an aligner in the lithographic process, the TEG information database 106 c which stores the information about various TEG for evaluating the characteristics with regard to circuits and processes, and the manufacturing cost information database 108 storing the information on the manufacturing cost. However, these are nothing but mere examples of databases, and in the actual design work, the designer may refers to more various databases other than the mentioned above, for instance an aligner information database etc.

First Preferred Embodiment

[0024] A first preferred embodiment of the invention will now be described in the following with reference to FIG. 2. With this embodiment, it will be made clear how the LSI floor plan is established by referring to a LSI chip yield per wafer and a manufacturing cost per LSI chip, which are calculated by using the CAD device as shown in FIG. 1.

[0025] After activating the CAD device for use in the floor planning work (step S101), a temporary LSI chip size for the floor plan is selected from the basic design information database 104 provided in the CAD device (step S102). The control device 102 then refers to the process information, the mark information, the TEG information, etc. as stored in the databases 106 a, 106 b, 160 c, . . . etc. based on the above temporary LSI chip size, and executes a simulation of LSI layout on the wafer under the same condition as in the actual LSI chip production, namely by arranging on the wafer not only LSI chips but also other objective components such as various marks, TEG, etc. (step S103).

[0026] In this stage, the control device 102 judges whether or not all the constituents including LSI chips, various marks, TEG, etc. can be arranged on the wafer under the conditions instructed by the designer (step S104). If it is judged that all the constituents can not be arranged on the wafer, the control device 102 informs the designer through the display device 110 that the arrangement is not possible under his instructed conditions, and returns to the step S101. Taking account of this result, the designer revises his initially selected conditions, provides new selection of conditions and again tries to perform another simulation of the LSI layout under the renewed conditions to examine whether or not all the constituents can be arranged on the wafer as intended.

[0027] Contrary to this, if it is judged at the step S104 that all the constituents including LSI chips, various marks, TEG, etc. can be successfully arranged on the wafer, the control device 102 then calculates a LSI chip yield per wafer from the number of LSI chips located on the wafer (step S105). The control device 102 further refers to the manufacturing cost information stored in the manufacturing cost information database 108, and calculates a manufacturing cost under the current condition (step S106), and further calculates a manufacturing cost per LSI chip (step S107). The information on the LSI chip yield per wafer and the manufacturing cost per LSI chip as obtained in this way, is notified to the designer through the display device 101 (step S108). If the result of the above simulation is satisfactorily acceptable in view of the manufacturing cost, the designer may terminate his LSI floor plan. If, however, the result is still not acceptable in view of the manufacturing cost, the designer returns to the step S101, revises various design conditions, and again perform the simulation with regard to the arrangement of LSI chips and other various constituents on the wafer.

[0028] As described in the above, according to the first embodiment of the method of LSI layout of the invention, the designer is able to grasp the LSI chip yield per wafer and the manufacturing cost per LSI chip in connection with his selected chip size, substantially on the real time basis in the stage of his working on the LSI layout prior to entering in the mask design process. Accordingly, the designer may judge with ease how much the LSI chip is to be downsized for the efficient LSI layout.

Second Preferred Embodiment

[0029] In the next, a second preferred embodiment of the invention will be described in the following, with reference to FIG. 3. In this embodiment, it will be described how the LSI floor plan is established, in case that the LSI chip size is changed in the stage of making the floor plan, by referring to the LSI chip yield per wafer and the manufacturing cost per LSI chip, which are calculated by means of the CAD device as showing in FIG. 1.

[0030] At first, the CAD device for use in the floor planning work is activated (step S201). Then, a temporary LSI chip size for the floor plan is selected from the basic design information database 104 provided in the CAD device (step S202). Then, the control device 102 refers to the process information, the mark information, the TEG information, etc. as stored in the databases 106 a, 106 b, 106 c, . . . etc. based on the above temporary LSI chip size, and executes a simulation of the LSI layout on the wafer under the same condition as in the actual LSI chip production, namely, by arranging on the wafer not only LSI chips but also other objective components such as various marks, TEG, etc. (step S203).

[0031] In the next, the control device 102 judges whether or not all the constituents including LSI chips, various marks, TEG, etc. can be arranged on the wafer under the conditions set by the designer (step S204). If it is judged that all the constituents can not be located on the wafer, the control device 102 calculates neither LSI chip yield per wafer nor manufacturing cost per LSI chip with regard to the temporarily chip size as selected at that time, and just skips over to the step for revising the LSI chip size (step S208).

[0032] Contrary to this, if it is judged at a step S204 that all the constituents including LSI chips, various marks, TEG, etc. can be successfully arranged on the wafer, the control device 102 calculates a LSI chip yield per wafer (step S205). The control device 102 further refers to the manufacturing cost information stored in the manufacturing cost information database 108, and calculates a manufacturing cost under the current condition (step S206) and further calculates a manufacturing cost per LSI chip (step S207).

[0033] Then, the control device 102 revises the LSI chip size (step S208) according to the designer's designated conditions. Change of the chip size may be carried out in various ways, for instance changing the chip size (a) by keeping the lateral chip side length constant, (b) by keeping the vertical chip side length constant, (c) by keeping the chip area constant, or (d) by keeping a ratio between the lateral chip side length and the vertical one constant.

[0034] Then, it is examined whether or not the revised chip size falls within a tolerable chip size range as designated by the designer (step S210). If the revised chip size falls within the tolerable chip size range, it is notified to the designer through the display 110 along with the LSI chip yield per wafer and the manufacturing cost per chip, which are calculated in association therewith. Contrary to this, if the revised LSI chip size does not fall within the tolerable chip size range, it is repeatedly processed by the steps S203 through S208 until it can fall within the above range. Through the above procedure, the designer finally selects an optimum chip size from the value obtained therefrom and terminates his LSI floor plan.

[0035] As described in the above, according to the 2nd embodiment of the invention, in the stage of making the LSI floor plan, the LSI chip yield per wafer and the manufacturing cost per chip can be simulated with the chip size which is variously changed, and the result of the simulation is notified to the designer, so that the designer can select with ease an optimum LSI chip size under his preferably selected conditions.

Third Preferred Embodiment

[0036] In the next, the third embodiment of the method of LSI layout according to the present invention will be described in the following, with reference to FIG. 4. In the method of this embodiment, even after completion of entire arrangement including I/O cells and wiring, it becomes possible to examine whether or not an aimed LSI chip yield has been satisfactorily achieved.

[0037] The CAD device for use in the place and route work is activated first (step S301). Then, an actual LSI chip size after arrangement of LSI chips, other objective components and wiring is selected from the basic design information database 104 provided in the CAD device (step S302). Next, the control device 102 refers to the process information, the mark information, the TEG information, etc. as stored in the databases 106 a, 106 b, 106 c, . . . etc. based on the above real LSI chip size, and executes a simulation of the LSI layout on the wafer under the same condition as in the actual LSI chip production, namely, by arranging on the wafer not only LSI chips but also other objective components such as various marks, TEG, etc. (step S303).

[0038] In this stage, the control device 102 judges whether or not all the constituents including LSI chips, various marks, TEG, etc. can be arranged on the wafer according to the conditions given by the designer (step S304). If it is judged that all the constituents can not be arranged on the wafer, the control device 102 informs the designer through the display device 100 that the arrangement is not possible under his given conditions, and returns to the step S301. Taking account of this result, the designer revises his initially given conditions to make the new selection of conditions, and again tries to perform another simulation of the LSI layout under the renewed conditions to examine whether or not all the constituents can be arranged on the wafer.

[0039] Contrary to this, if it is judged at the step S304 that all the constituents including LSI chips, various marks, TEG, etc. can be actually arranged on the wafer, the control device 102 calculates a LSI chip yield per wafer from the number of LSI chips arranged on the wafer (step S305). The control device 102 further refers to the necessary manufacturing cost information as stored in the manufacturing cost information database 108, and calculates a manufacturing cost under the conditions as currently set (step S306), and further calculates a manufacturing cost per LSI chip (step S307). The information on the LSI chip yield per wafer and the manufacturing cost per LSI chip as obtained in the way like this, is notified to the designer through the display device 110 (step S308). If the result of the above simulation is satisfactorily acceptable, the designer may terminate his LSI place and route. If, however, the result is still not acceptable, the designer returns to the step S301, revises various design conditions, and again executes the simulation with regard to the arrangement of LSI chips and other various constituents on the wafer.

[0040] As described in the above, according to the third embodiment of the method of LSI layout according to the invention, even after finishing entire arrangement including 1/0 cells and wiring, the designer can grasp on the real time basis, the possibility of chip arrangement on the wafer, the LSI chip yield per wafer, and the manufacturing cost per LSI chip in correspondence with the current real chip size, during his working on the LSI layout.

[0041] The invention has been discussed so far by way of several preferred embodiments of the method of LSI layout according to the invention. However, it should be noted that the invention is not limited by those embodiments, and it is clear that any one skilled in the art may make various changes and/or modifications of the invention without departing from the category of the technical thoughts as recited in the patent claims attached hereto, and needless to say, such changes and modifications apparently falls within the scope of the technical thoughts of the present invention.

[0042] As has been described, according to the invention, it is made possible, even when the design of LSI layout is going on, to examine whether or not LSI chips can be arranged on the wafer together with various marks, TEG, etc., with the currently selected chip size, so that it is possible to obviate the work for modifying the LSI layout which is caused in association with the result of the mask design.

[0043] Furthermore, according to the invention, it is made possible to obtain the information on the LSI chip yield per wafer and the manufacturing cost per chip in correspondence with the currently selected chip size, even when the design of LSI layout work is going on. Therefore, the invention makes it possible to quickly judge, under the limitation of the LSI development term, how much the LSI chip is to be downsized for an optimum LSI layout, and also to carry out the low cost conscious design of LSI layout.

[0044] The entire disclosure of Japanese Patent Application No. H9-153016 filed on May 26, 1997 including specification, claims, drawings and summary is incorporated herein by reference in its entirety. 

What is claimed is:
 1. A method of LSI layout which is used in the stage of making a LSI layout plan for each of a plurality of LSI chips before entering in the design of masks, wherein there is included a step of judging whether or not all the LSI chips can be arranged on a single wafer along with other objective components, based on a given LSI chip size and referring to the information on the other objective components.
 2. A method of LSI layout as claimed in claim 1, wherein the information on said other objective components includes the information on various marks and the information on TEG.
 3. A method of LSI layout as claimed in claim 1, wherein said given LSI chip size is temporarily calculated and defined based on basic design data.
 4. A method of LSI layout as claimed in claim 1, wherein said given LSI chip size is a actual LSI chip size after arrangement and wiring of all the LSI chips and other objective components on the wafer have been completed.
 5. A method of LSI layout as claimed in claim 1, wherein said given LSI chip size may includes a plurality of LSI chip sizes.
 6. A method of LSI layout which is used in the stage of making a LSI layout plan for each of a plurality of LSI chips before entering in the design of masks, wherein there is included a step of calculating a LSI chip yield per wafer based on a given LSI chip size.
 7. A method of LSI layout as claimed in claim 6, wherein said given LSI chip size is temporarily calculated and defined based on basic design data.
 8. A method of LSI layout as claimed in claim 6, wherein said given LSI chip size is a actual LSI chip size after arrangement and wiring of all the LSI chips and other objective components on the wafer have been completed.
 9. A method of LSI layout as claimed in claim 6, wherein said given LSI chip size may includes a plurality of LSI chip sizes.
 10. A method of LSI layout which is used in the stage of making a LSI layout plan for each of a plurality of LSI chips before entering in the design of masks, wherein there is included a step of calculating a manufacturing cost per LSI chip based on a given LSI chip size.
 11. A method of LSI layout as claimed in claim 10, wherein said given LSI chip size is temporarily calculated and defined based on basic design data.
 12. A method of LSI layout as claimed in claim 10, wherein said given LSI chip size is a actual LSI chip size after arrangement and wiring of all the LSI chips and other objective components on the wafer have been completed.
 13. A method of LSI layout as claimed in claim 10, wherein said given LSI chip size may includes a plurality of LSI chip sizes. 